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VN3205 N-Channel Enhancement-Mode Vertical DMOS FETs
Features
Free from secondary breakdown Low power drive requirement Ease of paralleling Low CISS and fast switching speeds Excellent thermal stability Integral SOURCE-DRAIN diode High input impedance and high gain Complementary N- and P-Channel devices
General Description
These enhancement-mode (normally-off) transistors utilize a vertical DMOS structure and Supertex's well-proven silicon-gate manufacturing process. This combination produces devices with the power handling capabilities of bipolar transistors and with the high input impedance and positive temperature coefficient inherent in MOS devices. Characteristic of all MOS structures, these devices are free from thermal runaway and thermally induced secondary breakdown. Supertex's vertical DMOS FETs are ideally suited to a wide range of switching and amplifying applications where high breakdown voltage, high input impedance, low input capacitance, and fast switching speeds are desired.
Applications
Motor controls Converters Amplifiers Switches Power supply circuits Drivers (relays, hammers, solenoids, lamps, memories, displays, bipolar transistors, etc.)
Ordering Information
Device VN3205 TO-92 VN3205N3-G 14-Lead PDIP VN3205P-G TO-243AA (SOT-89) VN3205N8-G Die(1) VN3205ND BVDSS/BVDGS
(V)
RDS(ON)
max ()
VGS(th)
max (V)
50
0.3
2.4
-G indicates package is RoHS compliant (`Green') Note: (1) MIL visual screening available.
Pin Configurations
DRAIN
SOURCE
Absolute Maximum Ratings
Parameter Drain to source voltage Drain to gate voltage Gate to source voltage Operating and storage temperature Soldering temperature* Value BVDSS BVDGS 20V -55C to +150C
DRAIN GATE
SOURCE DRAIN GATE
TO-92 (N3)
G3 S3 N/C S4 G4 D4
TO-243AA (SOT-89) (N8)
D3
+300C
Absolute Maximum Ratings are those values beyond which damage to the device may occur. Functional operation under these conditions is not implied. Continuous operation of the device at the absolute rating level may affect device reliability. All voltages are referenced to device ground. * Distance of 1.6mm from case for 10 seconds.
D1
D2 G2 S2 N/C S1 G1
14-Lead PDIP (P)
VN3205
Product Marking
VN 3205
YYWW
Top Marking
YY = Year Sealed WW = Week Sealed = "Green" Packaging
YYWW
VN3205P
LLLLLLLLLL
TO-92 (N3)
VN2LW
Bottom Marking
CCCCCCCCCCC AAA
YY = Year Sealed WW = Week Sealed L = Lot Number C = Country of Origin* A = Assembler ID* = "Green" Packaging
*May be part of top marking
W = Code for week sealed
TO-243AA (SOT-89) (N8)
14-Lead PDIP (P)
Thermal Characteristics
Package TO-92 14-Lead PDIP TO-243AA ID (continuous)*
(A)
ID (pulsed)
(A)
Power Dissipation @TC = 25OC
(W)
jc
( C/W)
O O
ja
( C/W)
IDR
(A)
IDRM
(A)
1.2 1.5 1.5
8.0 8.0 8.0
1.0 3.0 1.6 (TA = 25O)
125 41.6 15
170 83.3 78
1.2 1.5 1.5
8.0 8.0 8.0
Notes: * ID (continuous) is limited by max rated TJ, TA = 25OC. Total for package. Mounted on FR5 board, 25mm x 25mm x 1.57mm.
Electrical Characteristics (T = 25C unless otherwise specified)
A
Sym BVDSS VGS(th) VGS(th) IGSS
Parameter Drain-to-source breakdown voltage Gate threshold voltage Change in VGS(th) with temperature Gate body leakage current
Min 50 0.8 -
Typ -4.3 1.0 14 0.85 1.5
Max 2.4 -5.5 100 10 1.0 0.45 0.45 0.3 0.3 1.2 -
Units V V mV/ C nA A mA A
O
Conditions VGS = 0V, ID = 10mA VGS = VDS, ID = 10mA VGS = VDS, ID = 10mA VGS = 20V, VDS = 0V VGS = 0V, VDS = Max Rating VGS = 0V, VDS = 0.8 Max Rating, TA = 125OC VGS = 10V, VDS = 5.0V VGS = 4.5V, ID = 1.5A
IDSS
Zero gate voltage drain current -
ID(ON)
ON-state drain current TO-92 and PDIP
3.0 1.0
RDS(ON)
Static drain-to-source ON-state resistance
TO-243AA TO-92 and PDIP TO-243AA
VGS = 4.5V, ID = 0.75A VGS = 10V, ID = 3.0A VGS = 10V, ID = 1.5A
RDS(ON) GFS
Change in RDS(ON) with temperature Forward transconductance
%/ C mmho
O
VGS = 10V, ID = 3.0A VDS = 25V, ID = 2.0A
2
VN3205
Electrical Characteristics (cont.) (T = 25C unless otherwise specified)
A
Sym CISS COSS CRSS td(ON) tr td(OFF) tf VSD trr
Parameter Input capacitance Common source output capacitance Reverse transfer capacitance Turn-ON delay time Rise time Turn-OFF delay time Fall time Diode forward voltage drop Reverse recovery time
Min -
Typ 220 70 20 300
Max 300 120 30 10 15 25 25 1.6 -
Units
Conditions VGS = 0V, VDS = 25V, f = 1.0MHz
pF
ns
VDD = 25V, ID = 2.0A, RGEN = 10 VGS = 0V, ISD = 1.5A VGS = 0V, ISD = 1.0A
V ns
Notes: (1) All D.C. parameters 100% tested at 25OC unless otherwise stated. (Pulse test: 300s pulse, 2% duty cycle.) (2) All A.C. parameters sample tested.
Switching Waveforms and Test Circuit
10V
VDD RL OUTPUT
90% INPUT
0V
10%
t(ON)
PULSE GENERATOR
t(OFF) tr td(OFF) tF
RGEN
td(ON)
VDD
10%
10%
INPUT
D.U.T.
OUTPUT
0V
90%
90%
3
VN3205
Typical Performance Curves
Output Characteristics
20 20
Saturation Characteristics
VGS
16
10V
VGS
16
10V
ID (amperes)
ID (amperes)
12
8V
12
8V
8
6V
8
6V
4
4
4V 3V
0 0 10 20 30 40 50 0 0 2 4 6 8 10
4V 3V
VDS (volts) Transconductance vs. Drain Current
5 2.0
VDS (volts) Power Dissipation vs. Temperature
4
VDS = 25V
1.6
TO-243AA (T A = 25C) P-DIP
GFS (siemens)
TA = -55C
2
25C 125C
PD (watts)
3
1.2
0.8
TO-92
1
0.4
0 0 2 4 6 8 10
0 0 25 50 75 100 125 150
ID (amperes) Maximum Rated Safe Operating Area
10 TO-92 (pulsed) P-DIP (pulsed) 1.0 TO-243AA (pulsed)
TC (C) Thermal Response Characteristics
Thermal Resistance (normalized)
0.8
ID (amperes)
1.0 TO-243AA (DC) TO-92 (DC) P-DIP (DC) 0.1
TO-243AA
0.6
TA = 25C PD = 1.6W
0.4
TC = 25C
.01 0 1 10 100
0.2
TO-92 P D = 1W T C = 25C
0.01 0.1 1.0 10
0 0.001
VDS (volts)
t p (seconds)
4
VN3205
Typical Performance Curves (cont.)
BV DSS Variation with Temperature
1.1
On-Resistance vs. Drain Current
1.0
0.8
V GS = 4.5V
B V D S S ( norma liz e d)
R D S ( O N ) ( ohms )
0.6
V GS = 10V
1.0
0.4
0.2
0.9 -50 0 50 100 150
0 0 4 8 12 16 20
T j ( C) Transfer Characteristics
10
I D (amperes) V GS(th) and R
1.2 DS(ON)
Variation with Temperature
1.6
V DS = 25V
8
25C
6
1.0
1.2
125 C
4
0.9
1.0
2
0.8
V GS(th) @ 1mA
0.8
0 0 2 4 6 8 10
0.7 -50 0 50 100 150
0.6
V GS (volts) Capacitance vs. Drain-to-Source Voltage
400 10
T j (C) Gate Drive Dynamic Characteristics
f = 1MHz
8 300
V DS = 10V
C ( pic ofa ra ds )
V G S ( volts )
V DS = 40V
6
C ISS
200
325 pF
4
100
C OSS
C RSS
0 0 10 20 30 40
2
215 pF
0 0 1 2 3 4 5
V DS (volts)
Q G (nanocoulombs)
5
R D S ( O N ) ( norma liz e d)
V G S ( th) ( norma liz e d)
T A = -55 C
1.1
R DS(ON) @ 10V, 3A
1.4
I D ( a mpe re s )
VN3205
3-Lead TO-92 Package Outline (N3)
D
A Seating Plane 1 2 3
L
b e1 e
C
Front View
Side View
E1
E 1 2 3
Bottom View
Symbol MIN Dimension (inches) NOM MAX
Drawings not to scale.
A .170 .210
b .014 .022
C .014 .022
D .175 .205
E .125 .165
E1 .080 .105
e .095 .105
e1 .045 .055
L .500 -
6
VN3205
3-Lead TO-243AA (SOT-89) Package Outline (N8)
Symbol MIN Dimensions (mm) NOM MAX
A 1.40 1.60
b 0.44 0.56
b1 0.36 0.48
C 0.35 0.44
D 4.40 4.60
D1 1.62 1.83
E 2.29 2.60
E1 2.13 2.29
e 1.50 BSC
e1 3.00 BSC
H 3.94 4.25
L 0.89 1.20
JEDEC Registration TO-243, Variation AA, Issue C, July 1986. Drawings not to scale.
7
VN3205
14-Lead PDIP (.300in Row Spacing) Package Outline (P)
.750x.250in body, .210in height (max), .100in pitch
D 14
Note 1 (Index Area)
E1
E b2
1 D1 D1 b
Top View
View B A
View B
A L
A2 A1 e
Seating Plane
eA A eB
Front View
View AA
Note 1: A Pin 1 identifier must be located in the index area indicated.The Pin 1 identifier may be either a mold, or an embedded metal or marked feature.
Symbol MIN Dimension (inches) NOM MAX
A .130 .210
A1 .015 .095
A2 .115 .130 .195
b .014 .018 .022
b2 .045 .060 .070
D .735 .750 .775
D1 .005 .065
E .300 .310 .325
E1 .240 .250 .280
e .100 BSC
eA .300 BSC
eB .300 .430
L .115 .130 .150
JEDEC Registration MS-001, Variation AA, Issue D, June, 1993. Drawings not to scale.
(The package drawing(s) in this data sheet may not reflect the most current specifications. For the latest package outline information go to http://www.supertex.com/packaging.html.)
Doc.# DSFP-VN3205 A101507
8

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